Microprocessor architecture: 2 L Internal architecture, Programming model [1] Article 2.1 Page 51 to 58
Memory Addressing: 6L Real mode and protected mode operation, Program invisible register [1] Article 2.2-2.3 Page 58 to 68
Addressing modes: 5 L Data addressing modes, Program memory addressing modes and Stack memory addressing modes [1] Article 3.1-3.3 Page 78 to 105
Microprocessor programming: 8L Machine language, Instruction formats, String data transfer instructions, Program control instructions, Assembly language programming [1] Article 4.1-4.5, 6.1-6.3 Page 112 to 142, 192 to 212
8088/8086 Hardware Specifications : 6L Pin-outs and pin functions, Clock generator, Bus buffering and latching, bus timing [1] Article 9.1-9.5 Page 302 to 322
Memory Interfacing: 6L Memory address decoding, 8-bit and 16-bit memory interfacing. [1] Article 10.2-10.4 Page 340 to 363
I/O interfacing: 7L Introduction to I/O interface, address decoding, Programmable Peripheral Interface, Timer [1] Article 11.1 (Up to page 380), 11.2, 11.3, 11.4 Page 377 to 379, 387-398, 414- 420, 423-428
Interrupts & Direct Memory Access 8L Interrupt controller, DMA controller [1]Article 12.1- 12.2, 13.1-13.2 (Up to page 516) Page 451 to 465, 490 to 506
Recommended Reading Material
Text Books 1. Barry B. Brey, The Intel Microprocessors : Architecture, Programming and Interfacing. 8th edition, Pearson Education, 2009
(8th Edition) Barry B. Brey-The Intel Microprocessors-Prentice Hall (2008)(1)
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